The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for forming a metal pattern using a hard mask and a method for forming a gate electrode in a semiconductor device using the same.
A polysilicon layer has been typically used as a gate electrode in a metal-oxide semiconductor (MOS) transistor. Such polysilicon gate electrode shows an advantage of a stable formation process. However, various patterns, including the gate electrode, have become micronized as semiconductor devices have become highly integrated. The recent micronization has reached a line width of 0.15 μm or less. Doped polysilicon, which has been used in a typical gate electrode formation, has a long delay time due to its high resistivity characteristic. Thus, it is difficult to apply the doped polysilicon in a device demanding a high speed operation.
Such difficulty has been raised as a serious limitation as semiconductor devices have become highly integrated. Thus, extensive research and developments have been recently made on an improved technology for forming a gate electrode by forming a high-melting point metal, such as tungsten (W), over polysilicon.
A typical method for forming a gate electrode in a semiconductor device using a polysilicon layer and a high-melting point metal as a gate electrode is briefly described as follows. Polysilicon and tungsten are formed as gate electrode materials over a substrate. A hard mask comprising a nitride-based layer is formed over the gate electrode. An amorphous carbon layer and a silicon oxynitride (SiON) layer functioning as an anti-reflective coating layer are formed over the hard mask. A photoresist pattern is formed over the resultant structure.
An etch process is performed to etch the anti-reflective coating layer using the photoresist pattern as an etch mask to form an anti-reflective coating pattern. Another etch process is performed to etch the hard mask using the anti-reflective coating pattern as an etch mask to form a hard mask pattern. The tungsten is etched using the hard mask pattern as an etch mask to form a gate electrode.
However, the typical method for forming a gate electrode in a semiconductor device generally shows the following limitations. A portion of the tungsten may be abnormally etched due to a low selectivity between the hard mask including the nitride-based layer and the tungsten when forming the hard mask pattern. Thus, a crack may be generated. The low selectivity between the nitride-based layer and the tungsten refers to almost not having a selectivity due to a very small difference in etch rates between the nitride-based layer and the tungsten.
FIGS. 1 and 2 illustrate micrographic views of cracks (as represented with reference denotation ‘A’) generated on a tungsten surface when a typical method for forming a gate electrode in a semiconductor device is applied. In particular, FIG. 1 illustrates a crack generated on a tungsten surface having a columnar rod crystal structure. The crack is often generated on the tungsten surface having the columnar rod crystal structure.
The crack generated on the tungsten surface causes an abnormally large damage on polysilicon during a subsequent etching of the polysilicon. Thus, a wedge-shaped damage may result or a pin hole may be induced in a peripheral region. The peripheral region refers to a certain region other than a region where a memory cell of a semiconductor device will be formed. Driving devices for driving the memory cell are formed in the peripheral region.
FIG. 3 illustrates a micrographic view of a wedge-shaped polysilicon damage (as represented with reference denotation ‘B’). FIG. 4 illustrates a micrographic view of a pin hole (as represented with reference denotation ‘C’) generated in a peripheral region. Such polysilicon damage and pin hole generation may induce a short circuit between a contact plug and a gate electrode during a subsequent contact plug formation process. Thus, a yield may be substantially reduced. FIG. 5 illustrates a micrographic view of a wafer surface on which a short circuit is generated between a contact plug and a gate electrode.